1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems incorporating a floating point unit.
2. Description of the Prior Art
It is known to provide data processing systems including a floating point unit. Within such floating point units it is known to provide multiply-accumulate operations of the form B+(A*C). These multiply-accumulate operations are strongly advantageous when performing digital signal processing operations, such as FIR filter functions. Whilst the ability to perform a multiply-accumulate as a single operation reduces code size and increases speed, a disadvantage is that the size of the circuits required within the floating point unit increases. Increasing the size of the required circuits is disadvantageous as it makes the system more expensive and consume more power.
Within floating point units providing multiply-accumulate operations, the addend B is aligned with the product (A*C) before the accumulate is performed by an adder. It is desirable from a circuit size point of view that the adder should be no wider than needed to sum the overlapping portions of the aligned-addend B' and the product (A*C). If there are high order bits within the two inputs to be added that extend above the width of the adder, then the carry output of the adder can be used determine whether or not these high order bits should be incremented. An incrementer responsive to such a carry output may then be provided in order to perform the possible increment of the high order bits. This incrementer is a large circuit element.
It is also known within floating point units to reduce the size of the multiplier by techniques such as "double-pumping", whereby the output is calculated over two processing cycles to obtain a full-width result with the output after the first cycle being recirculated through the multiplier.